中文 | English
Hefei University of Technology Logo J. Hefei Univ. Tech. (Nat. Sci.)

Navigation

An $ I^{2}C $ interface circuit with self-calibration and self-control function

Download Full Text

一种具有自校准、自控制功能的 $ I^{2}C $接口电路

Journal Information

J. Hefei Univ. Tech. (Nat. Sci.), May.2023, Vol.46 No.5: 641-645

DOI: 10.3969/j.issn.1003-5060.2023.05.011

Authors

ZHENG Shuangshuang $ ^{1} $, LIU Xinghui $ ^{1} $, ZHANG Wenjing $ ^{2} $, ZHANG Jianlong $ ^{2} $, YIN Feifei $ ^{1} $

(1. School of Physics, Liaoning University, Shenyang 110036, China; 2. Beijing Hongsi Electronic Technology Co., Ltd., Beijing 100085, China)

Abstract and Keywords

Abstract: A design for achieving the high performance inter-integrated circuit( $ I^{2}C $) interface through hardware self-detection and self-calibration in open-drain mode is proposed, and a method of $ I^{2}C $ interface self-control to achieve open-drain function is introduced. Based on the traditional $ I^{2}C $ interface circuit design, the function of self-detection of pull-down of the clock bus and self-calibration is added, which enables the hardware to automatically detect the low level of clock bus in the pull-up process and automatically calibrate its high level in open-drain mode, achieving performance improvement on the basis of improving communication stability. Taking into account different applications, an open-drain enable control circuit is added in order to improve the portability of IP, $ I^{2}C $ interface can self-control the open-drain function, support the software configuration, and be flexibly applied to a variety of general-purpose input/output(GPIO) models. The test of the finished development board circuit shows that when the system clock is 120 MHz, the bit rate in high-speed communication in open-drain mode is as high as 5.98 Mbit/s, and the bit rate in ultra-fast communication in push-pull mode is up to 30.00 Mbit/s.

Keywords: inter-integrated circuit( $ I^{2}C $) interface circuit; self-calibration; Verilog hardware description language(Verilog HDL); open-drain output; self-control

作者信息

郑双双 $ ^{1} $，刘兴辉 $ ^{1} $，张文婧 $ ^{2} $，张建龙 $ ^{2} $，尹飞飞 $ ^{1} $

(1. 辽宁大学 物理学院, 辽宁 沈阳 110036; 2. 北京宏思电子技术有限责任公司, 北京 100085)

摘要和关键词

摘要: 文章提出一种在开漏模式下通过硬件自检测、自校准实现高性能F $ ^{C} $(inter-integrated circuit)接口的设计, 并给出一种F $ ^{C} $接口自控制实现开漏功能的方法。在传统F $ ^{C} $接口电路的基础上, 增加了自检测拉低时钟总线并进行自校准的功能, 使得在开漏模式下, 硬件能够自动检测到时钟总线在上拉过程中的低电平并进行自校准高电平, 在改善通信稳定性的基础上实现了性能提升。考虑到不同的应用场合, 增加了开漏使能控制电路, 为提高IP的可移植性, F $ ^{C} $接口可自控制开漏功能, 支持软件配置, 灵活地应用于各种通用输入输出(general-purpose input/output, GPIO)模型中。成品开发板电路测试表明, 在系统时钟为120 MHz时, 该电路在开漏模式下高速通信中的位速率高达5.98 Mbit/s, 在推挽模式下超快速通信中的位速率高达30.00 Mbit/s。

关键词: $ I^{2}C $ 接口电路；自校准；Verilog HDL 语言；开漏输出；自控制

Funding

辽宁省自然科学基金资助项目（2021-MS-148）

Previous Next
Back to Contents

Account

Submission Login Reviewer Login Editor Login