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J. Hefei Univ. Tech. (Nat. Sci.)

合肥工业大学学报(自然科学版)

JOURNAL OF HEFEI UNIVERSITY OF TECHNOLOGY (NATURAL SCIENCE)

Competent Authorities: Ministry of Education of the People's Republic of China

Sponsor by: Hefei University of Technology

ISSN 1000-1646, CN 34-1001/N

Research on multi-issued dynamic scheduling controller of heterogeneous multi-core processor

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异构多核处理器多发射动态调度技术研究

Journal Information

J. Hefei Univ. Tech. (Nat. Sci.), May.2023, Vol.46 No.5: 632-640

DOI: 10.3969/j.issn.1003-5060.2023.05.010

Authors

TANG Xu, ZHANG Duoli, WANG Jie, SONG Yukun

(School of Microelectronics, Hefei University of Technology, Hefei 230601, China)

Abstract and Keywords

Abstract: With the continuous increase in the number of integrated cores on multi-core processors, the scheduling of parallel tasks has increasingly become a key factor restricting performance improvement. This paper designs a dynamic task scheduling controller for heterogeneous multi-core computing systems, which mainly realizes the functions of dynamic monitoring of the load of the processing unit, dynamic task wake-up, out-of-order task issue, task write-back security management and other functions. This paper studies a method to reduce the times of the result of a computing task written back to the double data rate (DDR) external memory, which greatly saves the memory access overhead and further improves the calculation performance. Simulation and performance tests show that in typical application scenarios, compared with the existing task issue controller without dynamic scheduling function, it has realized the transition from explicitly parallel programming to task parallel automatic control, and the programming friendliness is significantly improved. In different cases, the computing performance was improved by 11.3% to 37.9%.

Keywords: heterogeneous multi-core processor; dynamic task scheduling; out-of-order multiple issue; programming friendliness; on-chip network; on-chip node cache

作者信息

唐旭，张多利，王杰，宋宇鲲

（合肥工业大学微电子学院，安徽合肥230601）

摘要和关键词

摘要: 随着多核处理器片上集成核数的不断增多,并行任务的调度能力越来越成为制约性能提升的关键因素。文章设计一种面向异构多核计算系统的动态任务调度控制器,主要实现动态监控处理单元的负载情况、动态任务唤醒、乱序任务发射、任务写回安全管理等功能;研究一种降低计算任务结果数据回写双倍数据速率(double data rate, DDR)外存储器次数的方法,大幅节省了访存开销,进一步提升了计算性能。仿真及性能测试显示,在典型应用场景下,与已有的无动态调度功能的任务发射控制器相比,实现了显示并行化编程向任务并行的自动化控制过渡,编程友好度显著提高,在不同类型的测试案例中,分别提升了11.3%~37.9%的计算性能。

关键词: 异构多核处理器；动态任务调度；乱序多发射；编程友好；片上网络；片上节点缓存

Funding

国家自然科学基金资助项目（61874156）；安徽省高校协同创新资助项目（GXXT-2019-030）

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