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A level shifter design with immunity to dV/dt noise

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一种具有抗 dV/dt 噪声能力的电平位移电路设计

Journal Information

J. Hefei Univ. Tech. (Nat. Sci.), Nov.2025, Vol.48 No.11: 1466-1471

DOI: 10.3969/j.issn.1003-5060.2025.11.005

Authors

LUO Bo $ ^{1} $, CHENG Xin $ ^{1} $, MING Xiaohui $ ^{2} $

(1. School of Microelectronics, Hefei University of Technology, Hefei 230601, China; 2. Lakesemi Technology Co., Ltd., Hefei 230088, China)

Abstract and Keywords

Abstract: In half-bridge or full-bridge circuits, it is necessary to utilize level shifters to convert signals from the low-voltage rail to the high-voltage rail. During this process, rapidly changing floating grounds generate dV/dt noise, which couples through the bootstrap capacitor to the output of the level shifter. Once the noise reaches the trigger threshold of the latch, it can trigger the latch, resulting in an erroneous output signal. This paper presents a design incorporating a bypass current mirror and differential current compensation techniques to minimize noise currents and enhance noise immunity performance. The paper is based on a $ 0.4 \mu m $ BCD process, utilizing lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOS) with a breakdown voltage of 40 V as isolation device. The proposed design was verified using the Cadence simulation platform. The results show that the rise time response for the low-voltage rail signal is 0.852 ns, while the fall time response is 1.072 ns, demonstrating excellent matching between the rise and fall edges. Moreover, the level shifter exhibits a dV/dt noise immunity capability of 114 V/ns, significantly improving its reliability.

Keywords: level shift; common mode noise rejection; gate drive; current mirror; current compensation

作者信息

罗波 $ ^{1} $，程心 $ ^{1} $，明小慧 $ ^{2} $

(1. 合肥工业大学微电子学院，安徽合肥 230601；2. 仙湖半导体科技有限公司，安徽合肥 230088)

摘要和关键词

摘要: 在半桥或全桥电路中, 需要利用电平位移电路将低压轨的信号转换至高压轨, 该过程快速变化的浮动地带来 dV/dt 噪声, 并通过自举电容耦合到电平位移电路输出端, 一旦达到锁存器触发阈值将触发锁存器, 输出错误信号。文章通过设计旁路电流镜以及加入差分电流补偿的方法减小噪声电流, 提高噪声抑制性能; 基于 $ 0.4 \mu m $ BCD 工艺, 采用耐压 40 V 的横向双扩散金属氧化物半导体场效应晶体管 (lateral double-diffused metal-oxide-semiconductor field-effect transistor, LDMOS) 作为隔离器件, 利用 Cadence 仿真平台进行验证。结果表明: 低压轨信号的上升沿响应延时 0.852 ns, 下降沿响应延时 1.072 ns, 上升沿与下降沿的延时匹配较好; dV/dt 噪声的抑制能力为 114 V/ns, 可靠性显著提高。

关键词: 电平位移；共模噪声抑制；栅极驱动；电流镜；电流补偿

Funding

安徽省重点研究与开发计划资助项目（202304a05020021）

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