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A high-speed comparator based on MIPI D-PHY physical layer

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一种基于 MIPI D-PHY 物理层的高速比较器

Journal Information

J. Hefei Univ. Tech. (Nat. Sci.), Mar.2024, Vol.47 No.3: 360-366

DOI: 10.3969/j.issn.1003-5060.2024.03.012

Authors

ZHANG Xinyao $ ^{1,2} $, HUANG Zunkai $ ^{1} $, WANG Hui $ ^{1} $, TIAN Li $ ^{1} $, WANG Ning $ ^{1} $, FENG Songlin $ ^{1} $

(1. Shanghai Advanced Research Institute, Chinese Academy of Sciences, Shanghai 201210, China; 2. School of Integrated Circuits, University of Chinese Academy of Sciences, Beijing 100049, China)

Abstract and Keywords

Abstract: Based on the MIPI D-PHY physical layer transmission protocol, a high-speed and low-power self-biased comparator circuit is designed, and the circuit is theoretically analyzed and simulated. The overall structure of comparator is composed of two stages of op-amps; the common gate, the common source and the NMOS transistor working in the linear region form the first-stage amplification structure, and the op-amp with the current source as the load forms the second-stage amplification structure. The differential signal is input through the NMOS source, which improves the common-mode voltage receiving range of the signal. There is no additional current source bias in the circuit structure, which improves the data transmission rate and reduces power consumption. The circuit is designed based on SMIC 0.18 $ \mu $m CMOS process, powered by 1.8 V voltage. Simulation results show that the high-speed comparator can accurately receive differential signals with low common-mode voltage, the DC gain is 37.4 dB, and the transmission rate reaches 2.5 Gb/s; the power consumption is 326 $ \mu $W/(Gb/s); the common-mode voltage range of the received differential signal reaches 30-330 mV.

Keywords: mobile industry processor interface (MIPI); high-speed receiving circuit; MIPI D-PHY physical layer; CMOS image sensor; high-speed comparator

作者信息

张欣瑶 $ ^{1,2} $，黄尊恺 $ ^{1} $，汪辉 $ ^{1} $，田犁 $ ^{1} $，汪宁 $ ^{1} $，封松林 $ ^{1} $

(1. 中国科学院上海高等研究院，上海 201210；2. 中国科学院大学集成电路学院，北京 100049)

摘要和关键词

摘要: 基于 MIPI D-PHY 物理层传输协议, 文章设计一种高速低功耗的自偏置比较器电路, 并对电路进行理论分析和仿真验证。该高速比较器总体结构由二级运放构成: 共栅极和共源极以及工作在线性区的 NMOS 管组成第 1 级放大结构; 电流源作负载的四管运放组成第 2 级放大结构。差分信号通过 NMOS 源极进行输入, 提升信号的共模电压接收范围。电路结构中无额外电流源偏置, 提高数据传输速率的同时减小了功耗。基于 SMIC 0.18 $ \mu $m CMOS 工艺设计, 采用 1.8 V 电压供电, 仿真结果表明: 高速比较器能准确接收低共模电平的差分信号, 直流增益为 37.4 dB, 传输速率达到 2.5 Gb/s, 功耗达到 326 $ \mu $W/(Gb/s), 可以接收到差分信号的共模电平范围为 30~330 mV。

关键词: 移动产业处理器接口（MIPI）；高速接收电路；MIPI D-PHY 物理层；CMOS 图像传感器；高速比较器 中图分类号：TN432 文献标志码：A 文章编号：1003-5060（2024）03-0360-07

Funding

国家重点研发计划资助项目（2021YFB2206302）；国家自然科学基金资助项目（62004201）

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