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J. Hefei Univ. Tech. (Nat. Sci.)

合肥工业大学学报(自然科学版)

JOURNAL OF HEFEI UNIVERSITY OF TECHNOLOGY (NATURAL SCIENCE)

Competent Authorities: Ministry of Education of the People's Republic of China

Sponsor by: Hefei University of Technology

ISSN 1000-1646, CN 34-1001/N

A high-throughput BP decoder based on precomputation units

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一种基于预计算单元的高吞吐率 BP 译码器

Journal Information

J. Hefei Univ. Tech. (Nat. Sci.), Feb.2026, Vol.49 No.2: 180-186

DOI: 10.3969/j.issn.1003-5060.2026.02.006

Authors

GUO Wenjie, DU Gaoming, CAO Zihuan, WANG Xiaolei, LI Zhenmin

(School of Microelectronics, Hefei University of Technology, Hefei 230601, China)

Abstract and Keywords

Abstract: To address the issues of excessive resource consumption and long critical paths in existing architectures, this paper proposes a fully pipelined polar code belief propagation (BP) decoder architecture based on precomputation units. This architecture employs different precomputation units at different pipeline stages, reducing hardware resources without compromising decoding performance. A novel arithmetic unit is introduced for logical operations, which shortens the longest critical path and enables higher decoder operating frequencies. By eliminating the need for early termination of iterations and omitting computations for certain pipeline stages, the design reduces the number of pipeline stages without affecting decoding performance. The synthesis results on the TSMC 28 nm process indicate that the designed decoder, with a code length of 512, occupies an area of $ 2.98 \, mm^2 $, operates at a frequency of $ 3 \, MHz $, and achieves a resource efficiency of $ 572.6 \, \text{(Gbit/s)} / \text{mm}^2 $. Comparisons with existing polar code decoder architectures demonstrate varying degrees of improvement.

Keywords: polar code decoder; 6th generation mobile networks; throughput; resource efficiency; application-specific integrated circuit

作者信息

郭文杰，杜高明，曹子桓，王晓蕾，李桢旻

（合肥工业大学微电子学院，安徽合肥230601）

摘要和关键词

摘要: 针对现有全流水极化码置信传播译码器存在的资源消耗过大和最长关键路径较长的问题, 文章设计一种基于预计算的全流水置信传播译码器架构, 该架构在不同的流水线阶段采用不同的预计算单元, 在减少硬件资源的同时不影响译码器的译码性能。通过采用新型运算单元进行逻辑运算, 有效缩短了关键路径, 提高了译码器工作频率; 由于无需提前终止迭代, 取消了部分流水线阶段的运算, 实现了降低流水线阶段数的同时也未影响译码器的译码性能。在 TSMC 28 nm 工艺下的综合结果表明, 所设计的译码器在码长为 512 的情况下, 面积大小为 2.98 mm², 工作频率为 333 MHz, 资源效率为 572.6 (Gbit/s)/mm², 相较于现有极化码译码器架构均有不同程度的提升。

关键词: 极化码译码器；第六代移动通信技术；吞吐率；资源效率；专用集成电路

Funding

国家重点研发计划资助项目（2018YFB2202604）；安徽省重点研究与开发计划资助项目（202104g01020008）

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