中文 | English

J. Hefei Univ. Tech. (Nat. Sci.)

合肥工业大学学报(自然科学版)

JOURNAL OF HEFEI UNIVERSITY OF TECHNOLOGY (NATURAL SCIENCE)

Competent Authorities: Ministry of Education of the People's Republic of China

Sponsor by: Hefei University of Technology

ISSN 1000-1646, CN 34-1001/N

Analysis and optimization of branch predictor based on OpenLA500

Download Full Text

基于 OpenLA500 的分支预测器分析与优化

Journal Information

J. Hefei Univ. Tech. (Nat. Sci.), Jun. 2026, Vol. 49 No. 6: 758-763

DOI: 10.3969/j.issn.1003-5060.2026.06.006

Authors

HE Junyi, YUAN Dongliang, LIU Shuai, ZHANG Min, WANG Lei, LI Jiahang

(School of Computer Science and Technology, Henan Polytechnic University, Jiaozuo 454000, China)

Abstract and Keywords

Abstract: Embedded microprocessors use many parallel techniques to achieve higher processor performance, and the increase in instruction parallelism makes high-precision branch predictors increasingly important. This paper takes the OpenLA500 processor core based on the LoongArch instruction set as the platform and adopts two different methods for branch prediction: Gshare predictor and hybrid predictor. By expanding the branch prediction entries, improving the utilization of branch history information, and using XOR processing for branch instruction addresses to reduce the probability of branch aliasing, the branch prediction capability of the original processor is enhanced. The optimized processors were simulated and verified using ten test programs, including CoreMark, and the prototype validation was carried out on Xilinx Artix-7 field-programmable gate array (FPGA). The experimental results show that the average prediction accuracy of the Gshare branch predictor and the hybrid predictor reached 91.87% and 93.23%, respectively, representing improvements of 3.22% and 4.58% over the original branch predictor.

Keywords: LoongArch instruction set; branch predictor; destructive aliasing; field-programmable gate array (FPGA)

作者信息

贺军义，袁东亮，刘帅，张敏，王磊，李佳航

（河南理工大学计算机科学与技术学院，河南焦作454000）

摘要和关键词

摘要: 嵌入式微处理器为获得更高的处理器性能使用了许多并行技术, 指令并行度的提高使得高精度的分支预测器变得越来越重要。文章以基于龙芯指令集 LoongArch 设计的 OpenLA500 处理器核心为平台, 分别采用 Gshare 预测器和混合预测器 2 种方式扩大分支预测表项, 提高分支历史信息的利用率, 并对分支指令地址进行异或处理来降低分支别名的概率, 从而提高原有处理器的分支预测能力。使用包括 CoreMark 在内的 10 项测试程序对优化前、后的处理器进行仿真验证, 并在 Xilinx Artix-7 现场可编程门阵列 (field-programmable gate array, FPGA) 上完成原型验证。实验结果表明, Gshare 分支预测器和混合预测器平均预测准确率分别达到 91.87% 和 93.23%, 相较优化前分别提高了 3.22% 和 4.58%。

关键词: LoongArch 指令集；分支预测器；别名问题；现场可编程门阵列（FPGA）

Funding

国家自然科学基金资助项目（61772159；61872126）；河南省科技攻关资助项目（242102210185）；河南省高校重点研究基金资助项目（20A520015）；河南省高校基本科研业务费专项资金资助项目（NSFRF240614）和河南理工大学博士基金资助项目（60907023）

Previous Next

Back to Contents