A design and implementation of a high speed 2-D sliding FFT

Journal Information

J. Hefei Univ. Tech. (Nat. Sci.), Jul.2023, Vol.46 No.7: 912-918

DOI: 10.3969/j.issn.1003-5060.2023.07.008

Authors

XU Dinghong $ ^{1,2} $, ZHANG Duoli $ ^{1,2} $, TAO Xiangying $ ^{1,2} $, HAN Shuaipeng $ ^{1,2} $, SONG Yukun $ ^{1,2} $

(1. School of Microelectronics, Hefei University of Technology, Hefei 230601, China; 2. IC Design Web-cooperation Research Center of Ministry of Education, Hefei 230601, China)

Abstract and Keywords

Abstract: This paper introduces the basic characteristic principles and hardware implementation of sliding fast Fourier transform (FFT) using 2-D FFT algorithm, and completes the application specific integrated circuit (ASIC) design of 2-D FFT with 256 window length and 16 step size. With the restriction of sequence integrity, the traditional FFT algorithm cannot meet the processing speed requirements of some high real-time signal analysis fields due to its large time delay. In this paper, sliding FFT algorithm is used to overcome the dependence of traditional FFT on sequence integrity. The sliding FFT processor uses 2-D FFT to compress the computation time of the new sequence, takes radix 16 butterfly arithmetic unit as the core, and adopts coefficient multiplexing and high radix Booth method to optimize coefficient coding technology, so as to compress the number of multipliers and reduce the circuit area. Compared with the traditional algorithm, the calculation time of single sliding window length of the designed 2-D sliding FFT is reduced by 16.1%. Compared with the result of MATLAB, the signal-to-noise ratio (SNR) of the 2-D sliding FFT is more than 130 dB. In the TSMC 28 nm process, the main frequency is 600 MHz and the area is 1 980 $ \mu $m×2 060 $ \mu $m.

Keywords: fast Fourier transform(FFT); sliding FFT; 2-D FFT algorithm; high-radix Booth coding

作者信息

许丁鸿 $ ^{1,2} $，张多利 $ ^{1,2} $，陶相颖 $ ^{1,2} $，韩帅鹏 $ ^{1,2} $，宋宇鲲 $ ^{1,2} $

(1. 合肥工业大学微电子学院, 安徽合肥 230601; 2. 教育部 IC 设计网上合作研究中心, 安徽合肥 230601)

摘要和关键词

摘要: 文章介绍了采用2-D快速傅里叶变换(fast Fourier transform, FFT)算法的滑动窗FFT的基本特性原理和硬件实现过程,完成了窗长256点、步长16点的2-D滑动窗FFT的专用集成电路(application specific integrated circuit, ASIC)设计。传统FFT算法受序列完整性的制约,时滞较大,无法满足某些高实时性信号分析领域的处理速度要求。该文采用滑动FFT算法,克服了传统FFT对序列完整性的依赖,设计的滑动FFT处理器使用2-D FFT压缩新序列计算时间,以基16蝶形运算器为核心,采用系数复用和高基Booth方法优化系数编码技术压缩乘法器的数量,减少电路面积。所设计的2-D滑动FFT完成单次滑动窗长的计算时间比传统算法节约了16.1%,变换结果与MATLAB的运算结果相比,信噪比(signal-to-noise ratio, SNR)大于130 dB。在TSMC 28 nm的工艺下,工作主频为600 MHz,面积为1980 μm×2060 μm。

关键词: 快速傅里叶变换(FFT)；滑动FFT；2-D FFT算法；高基Booth编码

Funding

国家自然科学基金资助项目（61874156）；安徽省高校协同创新资助项目（GXXT-2019-030）

合肥工业大学学报(自然科学版)

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