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Design and implementation of asymmetric numerical system algorithm based on SoC

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基于 SoC 的非对称数字系统算法设计与实现

Journal Information

J. Hefei Univ. Tech. (Nat. Sci.), May.2024, Vol.47 No.5: 655-659, 677

DOI: 10.3969/j.issn.1003-5060.2024.05.012

Authors

JIANG Zhi, XIAO Hao

(School of Microelectronics, Hefei University of Technology, Hefei 230601, China)

Abstract and Keywords

Abstract: An algorithm for achieving high-throughput finite state entropy (FSE) in System on Chip (SoC) is proposed. The performance of the proposed FSE encoder and decoder is compared to that of typical hardware Huffman coding (HC) in terms of compression ratio, speed, resource consumption, and power consumption. The results show that the proposed hardware FSE (hFSE) encoder and decoder have significant advantages over HC. The hFSE architecture is implemented on the processing system and programmable logic (PL) of an SoC, connected via the Advanced eXtensible Interface 4 (AXI4) bus. Algorithm tests demonstrate that FSE algorithm has better compression ratios for non-uniform data distributions and large data volumes. The encoder and decoder, which includes a configurable buffer module that outputs bit streams as single or double bytes to $ 4\ 096 \times 8 $-bit or $ 2\ 048 \times 16 $-bit block random access memory (BRAM), have been implemented on PL. The proposed FSE hardware architecture provides a low-power-consumption, low-resource-consumption and high-throughput hardware implementation for real-time compression applications.

Keywords: finite state entropy(FSE); Huffman coding(HC); System on Chip(SoC); high throughput; block random access memory(BRAM)

作者信息

姜智，肖昊

（合肥工业大学微电子学院，安徽合肥230601）

摘要和关键词

摘要: 文章提出一种在片上系统（System on Chip，SoC）实现高吞吐率的有限状态熵编码（finite state entropy，FSE）算法。通过压缩率、速度、资源消耗、功耗4个方面对所提出的编码器和解码器与典型的硬件哈夫曼编码（Huffman coding，HC）进行性能比较，结果表明，所提出的硬件FSE编码器和解码器具有显著优势。硬件FSE（hFSE）架构实现在SoC的处理系统和可编程逻辑块（programmable logic，PL）上，通过高级可扩展接口（Advanced eXtensible Interface 4，AXI4）总线连接SoC的处理系统和可编程逻辑块。算法测试显示，FSE算法在非均匀数据分布和大数据量情况下，具有更好的压缩率。该文设计的编码器和解码器已在可编程逻辑块上实现，其中包括1个可配置的缓冲模块，将比特流作为单字节或双字节配置输出到8bit位宽4096深度或16bit位宽2048深度的块随机访问存储器（block random access memory，BRAM）中。所提出的FSE硬件架构为实时压缩应用提供了高吞吐率、低功耗和低资源消耗的硬件实现。

关键词: 有限状态熵编码(FSE)；哈夫曼编码(HC)；片上系统(SoC)；高吞吐率；块随机访问存储器(BRAM)

Funding

国家自然科学基金资助项目（61974039）

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