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J. Hefei Univ. Tech. (Nat. Sci.)

合肥工业大学学报(自然科学版)

JOURNAL OF HEFEI UNIVERSITY OF TECHNOLOGY (NATURAL SCIENCE)

Competent Authorities: Ministry of Education of the People's Republic of China

Sponsor by: Hefei University of Technology

ISSN 1000-1646, CN 34-1001/N

Design and FPGA implementation of efficient polynomial multiplier based on NTT

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基于 NTT 的高效多项式乘法器设计及其 FPGA 实现

Journal Information

J. Hefei Univ. Tech. (Nat. Sci.), Nov.2024, Vol.47 No.11: 1498-1504

DOI: 10.3969/j.issn.1003-5060.2024.11.010

Authors

LIU Xiaofan, XIAO Hao, ZHAO Yanrui, HU Yue

(School of Microelectronics, Hefei University of Technology, Hefei 230601, China)

Abstract and Keywords

Abstract: Polynomial multiplication based on number theoretic transform(NTT) is an important component of post-quantum cryptography(PQC) and it is very important to improve the operation speed of polynomial multipliers. Based on field programmable gate array(FPGA), this paper proposed an efficient hardware acceleration scheme for polynomial multiplier with input bit width of 14 bits and length of 1 024, and designed a non-redundant and reusable butterfly unit circuit. By improving the parallelism of some operations, the utilization rate of modulo multiplier is close to 100%, and the iteration cycle of the whole polynomial multiplication is reduced and the overall operation speed is improved. The multiplier was finally deployed on Xilinx Artix-7 FPGA development board. The experimental results show that the maximum operating frequency of the circuit is 238 MHz, and the overall time of polynomial multiplication is 35.59 $ \mu $s. Compared with the existing hardware design, the algorithm efficiency of the proposed circuit is improved by 36.9%.

Keywords: post-quantum cryptography (PQC); polynomial multiplier; number theoretic transform (NTT); modular multiplication; field programmable gate array (FPGA)

作者信息

刘笑帆，肖昊，赵延睿，胡越

（合肥工业大学微电子学院，安徽合肥230601）

摘要和关键词

摘要: 基于快速数论变换(number theoretic transform, NTT)的多项式乘法运算是后量子密码(post-quantum cryptography, PQC)的重要组件, 提高多项式乘法器的运算速度至关重要。文章基于现场可编程门阵列(field programmable gate array, FPGA)提出一种输入位宽为14位、长度为1024的高效多项式乘法器硬件加速方案, 设计一种无冗余可重用的蝶形运算单元电路。通过提高部分运算的并行度, 实现模乘器接近100%的利用率, 降低整个多项式乘法运算的迭代周期, 提高整体运算速度。该乘法器最终被部署在Xilinx Artix-7 FPGA开发板上, 实验结果表明, 电路的最高工作频率为238 MHz, 多项式乘法运算的总体用时为35.59 $ \mu $s, 对比现有的硬件设计, 该文提出的电路运算效率提高36.9%。

关键词: 后量子密码（PQC）；多项式乘法器；快速数论变换（NTT）；模乘；现场可编程门阵列（FPGA）中图分类号：TN492 文献标志码：A 文章编号：1003-5060（2024）11-1498-07

Funding

国家自然科学基金资助项目（61974039）

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