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Hardware design and implementation of low-cost polynomial multiplier based on NTT in post-quantum cryptography

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后量子密码中基于 NTT 的 低成本多项式乘法器硬件设计与实现

Journal Information

J. Hefei Univ. Tech. (Nat. Sci.), Oct.2025, Vol.48 No.10: 1336-1343

DOI: 10.3969/j.issn.1003-5060.2025.10.006

Authors

KAN Ruichen, XIAO Hao

(School of Microelectronics, Hefei University of Technology, Hefei 230601, China)

Abstract and Keywords

Abstract: In post-quantum cryptography (PQC) algorithm CRISTALS-Kyber, polynomial multiplication takes up the main part. The number theoretic transform (NTT) can reduce the complexity of polynomial multiplication, so simple and efficient NTT architecture design is very important for the implementation of the whole algorithm. This paper proposes a hardware-friendly two-stage iterative address access algorithm for memory-based NTT/INTT, and designs a serial two-level iterative hardware architecture. In this architecture, when calculating NTT/INTT, half of the intermediate coefficients are provided by the butterfly unit (BFU), which saves BRAM quantity and simplifies the circuit structure. The architecture can also realize the sharing of NTT-INTT data streams, which further simplifies the control logic. In order to complete polynomial multiplication, a BFU is employed to complete the point-wise multiplication (PWM). The architecture was deployed on Xilinx Artix-7, and experimental results show that compared with the existing design, the proposed architecture reduces LUT, FF, BRAM resources by 30%, 23%, and 25%, respectively, and improves area-time product (ATP) performance by 10%-40%.

Keywords: post-quantum cryptography(PQC); Kyber algorithm; number theoretic transform(NTT); polynomial multiplier; memory access

作者信息

阚瑞晨，肖昊

（合肥工业大学微电子学院，安徽合肥230601）

摘要和关键词

摘要: 在后量子密码(post-quantum cryptography, PQC)算法 CRISTALS-Kyber 中, 多项式乘法计算占据主要部分, 而快速数论变换(number theoretic transform, NTT)可以降低多项式乘法的复杂度, 因此简洁高效的 NTT 架构设计对整个算法实现至关重要。文章针对基于存储器的 NTT/INTT 提出一种硬件友好的两级迭代地址访问算法, 并设计一种串行两级迭代硬件架构。该架构在计算 NTT/INTT 时 1/2 中间系数由前级蝶形单元(butterfly unit, BFU)提供, 以节省 BRAM 数量、简化电路结构, 并且能实现 NTT-INTT 数据流共用, 从而进一步简化控制逻辑; 为实现完整的多项式乘法, 设计配置 BFU 以完成对位系数相乘(point-wise multiplication, PWM)。该架构最终被部署在 Xilinx Artix-7 上, 运行结果表明, 与当前最先进设计相比, 文章设计的架构 LUT、FF、BRAM 资源分别减少了 30%、23%、25%, 且 ATP(area-time product)性能相较于已有设计提升了 10%~40%。

关键词: 后量子密码；Kyber算法；快速数论变换(NTT)；多项式乘法器；内存访问

Funding

国家自然科学基金资助项目（61974039）

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