基于两步式 TDC 的快速锁定全数字延迟锁相环的设计-学报杂志社

期刊信息

合肥工业大学（自然科学版），2026年7月，第49卷第7期：889-897

DOI: 10.3969/j.issn.1003-5060.2026.07.004

作者信息

王智源 $ ^{1} $，孟煦 $ ^{1,2} $

(1. 合肥工业大学微电子学院, 安徽合肥 230601; 2. 合肥工业大学教育部IC设计网上合作研究中心, 安徽合肥 230601)

摘要和关键词

摘要: 延迟锁相环(delay-lock loop, DLL)如今在高速通信领域有广泛应用, 其锁定时间是一个非常关键的指标。针对传统逐次比较型 DLL 锁定时间较长的问题, 文章提出一种基于两步式时间数字转换器(time-to-digital converter, TDC)的快速锁定全数字 DLL(all-digital DLL, ADDLL)。利用两步式 TDC 可快速测量 DLL 输入信号和反馈信号在传输路径上的延迟, 测量结束后将 TDC 产生的可用于调整 DLL 延迟线延迟的代码存入移位寄存器中; 继而鉴相器开始进行微调工作, 控制移位寄存器移位以调整延迟线延迟, 直至输入信号与反馈信号同相。文章在 TSMC 55 nm CMOS 工艺下完成了 DLL 设计与仿真, 结果表明, 所设计的 DLL 可在 20 个时钟周期内完成锁定。

关键词: 延迟锁相环(DLL)；两步式；时间数字转换器(TDC)；快速锁定；全数字

Authors

WANG Zhiyuan $ ^{1} $, MENG Xu $ ^{1,2} $

(1. School of Microelectronics, Hefei University of Technology, Hefei 230601, China; 2. IC Design Web-cooperation Research Center of Ministry of Education, Hefei University of Technology, Hefei 230601, China)

Abstract and Keywords

Abstract: Delay-lock loop (DLL) is widely used in high speed communication, in which the lock time is one of the key indicators. To address the long lock time in traditional DLL based on successive-approximation method, this paper presents a two-step time-to-digital converter (TDC)-based fast-lock all-digital DLL (ADDLL). Two-step TDC can reduce measurement time about the transmission delay between the input signal and feedback signal, and load the codes from TDC to shift register after the measurement, which can adjust the delay on delay line of DLL. Then, the phase detector starts to make fine adjustment for the codes in shift register by shifting them, until the locking of DLL. The design and simulation of the proposed DLL were performed based on TSMC 55 nm CMOS process. As shown in the simulation results, the maximum lock time of the proposed DLL is within 20 clock cycles.

Keywords: delay-lock loop(DLL); two-step; time-to-digital converter(TDC); fast-lock; all-digital

基金信息

国家重点研发计划资助项目（2023YFB4403804）

合肥工业大学学报(自然科学版)

导航菜单

基于两步式 TDC 的快速锁定全数字延迟锁相环的设计