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基于布局布线信息的单元间桥接缺陷测试方法

Test method for bridge defects between cells based on layout and routing information

期刊信息

合肥工业大学(自然科学版),2026年1月,第49卷第1期:49-55

DOI: 10.3969/j.issn.1003-5060.2026.01.007

作者信息

鲍善鑫,梁华国,胡杰文,邵志伟,章宏,鲁迎春

(合肥工业大学微电子学院,安徽合肥230601)

摘要和关键词

摘要: 随着集成电路工艺的不断迭代,桥接缺陷因导线密度增加出现得更加频繁。为了在测试中高效地覆盖更多桥接缺陷,文章提出一种基于布局布线信息的标准单元间桥接缺陷测试方法。该方法基于版图中的布局布线信息锁定单元外互连线间和相邻单元间的桥接高风险区域,并生成相应的故障模型以得到高质量的测试向量;通过采用基于桥接高风险区域长度的单元对生成策略和基于故障数量分布特点的缺陷阻值选择方法,测试效率得到进一步提高。实验结果表明:相较于四路桥接的测试方法,文章所提方法提高了约10.20%的测试覆盖率;相较于已提出的双单元测试方法,文章所提方法提高了约10.55%的测试覆盖率并降低了约60%的时间成本。

关键词: 桥接缺陷;缺陷仿真;故障模型;测试向量;测试覆盖率

Authors

BAO Shanxin, LIANG Huaguo, HU Jiewen, SHAO Zhiwei, ZHANG Hong, LU Yingchun

(School of Microelectronics, Hefei University of Technology, Hefei 230601, China)

Abstract and Keywords

Abstract: As the process of integrated circuits continues to iterate, bridge defects appear more frequently due to the increase in the density of wires. In order to efficiently cover more bridge defects in testing, a test method for bridge defects between standard cells based on layout and routing information is proposed in this paper. Bridge defects at two locations, between interconnecting wires outside cells and between neighboring cells, are targeted by the method using layout and routing information, and corresponding fault models are generated to obtain high-quality test patterns. Test efficiency is further improved by a strategy for generating cell pairs based on the length of the high-risk region of bridges and a method for selecting the resistance value of bridge defects based on the distribution of the number of faults. Experimental results show that compared to the four-way bridge test method, the method improves the test coverage by about 10.20%; compared to the previously proposed dual-cell test method, the method improves the test coverage by about 10.55% and reduces the time cost by about 60%.

Keywords: bridge defects; defect simulation; fault model; test patterns; test coverage

基金信息

国家重大科研仪器研制资助项目(62027815)

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