Abstract: As the process of integrated circuits continues to iterate, bridge defects appear more frequently due to the increase in the density of wires. In order to efficiently cover more bridge defects in testing, a test method for bridge defects between standard cells based on layout and routing information is proposed in this paper. Bridge defects at two locations, between interconnecting wires outside cells and between neighboring cells, are targeted by the method using layout and routing information, and corresponding fault models are generated to obtain high-quality test patterns. Test efficiency is further improved by a strategy for generating cell pairs based on the length of the high-risk region of bridges and a method for selecting the resistance value of bridge defects based on the distribution of the number of faults. Experimental results show that compared to the four-way bridge test method, the method improves the test coverage by about 10.20%; compared to the previously proposed dual-cell test method, the method improves the test coverage by about 10.55% and reduces the time cost by about 60%.
Keywords: bridge defects; defect simulation; fault model; test patterns; test coverage