合肥工业大学校徽

合肥工业大学学报自科版

合肥工业大学学报(自然科学版)

JOURNAL OF HEFEI UNIVERSITY OF TECHNOLOGY (NATURAL SCIENCE)

主管：中华人民共和国教育部

主办：合肥工业大学

ISSN 1003-5060, CN 34-1083/N

基于事务级协同仿真的 AXI4 交易器设计与验证

Design and verification of AXI4 transactor based on transaction-level co-emulation

期刊信息

合肥工业大学（自然科学版），2025年9月，第48卷第9期：1201-1207

DOI: 10.3969/j.issn.1003-5060.2025.09.007

作者信息

计润五 $ ^{1} $，黄正峰 $ ^{1} $，杨滔 $ ^{2} $，孙亮 $ ^{2} $

(1. 合肥工业大学微电子学院，安徽合肥 230601；2. 无锡亚科鸿禹电子有限公司，江苏无锡 214105)

摘要和关键词

摘要: 针对软硬件协同仿真过程中通信时间不同步和硬件仿真速度受限的难题，文章设计实现了一种高级可扩展接口（Advanced eXtensible Interface 4，AXI4）协议的交易器。基于事务级的软硬件协同仿真，结合硬件描述语言特性以及函数式编程的软件特性，使用 SpinalHDL 硬件描述语言设计一种 AXI4 接口协议的交易器，利用高级语言的敏捷特性对交易器生成流程进行高效处理，加速仿真验证阶段的编译流程。基于通用验证方法学（universal verification methodology，UVM）搭建验证平台对设计的交易器进行功能验证，结果显示交易器的代码覆盖率综合达到 99.17%，功能覆盖率达到 100%，符合交易器的功能要求。调用 AXI Interconnect IP 作为待测设计（design under test，DUT）在国产硬件仿真器-HyperSemu 上实现事务级传输，结果显示，相较于纯软件仿真加速比达 29.94，加快了协同仿真的验证速度，提升了仿真性能。

关键词: 交易器；高级可扩展接口（AXI4）；通用验证方法学（UVM）；硬件仿真器；SpinalHDL硬件描述语言

Authors

JI Runwu $ ^{1} $, HUANG Zhengfeng $ ^{1} $, YANG Tao $ ^{2} $, SUN Liang $ ^{2} $

(1. School of Microelectronics, Hefei University of Technology, Hefei 230601, China; 2. HyperSilicon Co., Ltd., Wuxi 214105, China)

Abstract and Keywords

Abstract: Aiming at the problems of unsynchronized communication time and limited hardware emulation speed in the process of software and hardware co-emulation, this paper designs and implements a transactor of Advanced eXtensible Interface 4(AXI4) protocol. Based on transaction-level software and hardware co-emulation, combined with the characteristics of hardware description language (HDL) and software features of functional programming, a transactor of AXI4 protocol is designed using SpinalHDL, which uses the agile features of high-level language to efficiently process the transaction generation process, and accelerates the compilation process of the emulation verification stage. Based on universal verification methodology (UVM), a verification platform was built to conduct functional verification on the designed transactor, and the results showed that the code coverage of the transactor comprehensively reached 99.17%, and the functional coverage reached 100%, meeting the functional requirements of the transactor. Using AXI Interconnect IP as design under test (DUT), transaction-level transmission was achieved on the domestic hardware emulator HyperSemu. Compared with VCS, the pure software simulation, the acceleration ratio reached 29.94, accelerating the verification speed of co-emulation and improving emulation performance.

Keywords: transactor; Advanced eXtensible Interface 4(AXI4); universal verification methodology (UVM); emulator; SpinalHDL

基金信息

国家自然科学基金资助项目（62274052；62374049）；安徽省重点研究与开发计划资助项目（202304a05020003）

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