Abstract: An algorithm for achieving high-throughput finite state entropy (FSE) in System on Chip (SoC) is proposed. The performance of the proposed FSE encoder and decoder is compared to that of typical hardware Huffman coding (HC) in terms of compression ratio, speed, resource consumption, and power consumption. The results show that the proposed hardware FSE (hFSE) encoder and decoder have significant advantages over HC. The hFSE architecture is implemented on the processing system and programmable logic (PL) of an SoC, connected via the Advanced eXtensible Interface 4 (AXI4) bus. Algorithm tests demonstrate that FSE algorithm has better compression ratios for non-uniform data distributions and large data volumes. The encoder and decoder, which includes a configurable buffer module that outputs bit streams as single or double bytes to $ 4\ 096 \times 8 $-bit or $ 2\ 048 \times 16 $-bit block random access memory (BRAM), have been implemented on PL. The proposed FSE hardware architecture provides a low-power-consumption, low-resource-consumption and high-throughput hardware implementation for real-time compression applications.
Keywords: finite state entropy(FSE); Huffman coding(HC); System on Chip(SoC); high throughput; block random access memory(BRAM)
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