一种应用于 DRAM 时钟电路的占空比校准器

文章设计了一种适用于动态随机存取存储器(dynamic random access memory, DRAM)时钟电路的占空比校准器, 可校准外部时钟输入和内部时钟传播时产生的占空比失真, 保证输出时钟的占空比接近50%。该设计针对DRAM工作频率范围过宽、传统的占空比校准器难以完全覆盖的问题, 采用时钟频率检测电路, 并在高频和低频时钟下对占空比校准器分别配置不同的检测精度和调节步长, 实现对宽工作频率范围的支持; 并基于19 nm存储工艺, 在1.1 V电压下进行仿真验证。仿真结果表明: 该占空比校准器的工作频率范围为400 MHz至2 GHz, 占空比校准范围为40.0%~60.0%, 校准精度为50.0%±1.0%; 在2 GHz频率下, 系统功耗为1.7 mW, 输出时钟峰峰值抖动为5.1 ps。

A duty cycle corrector (DCC) for clock circuits in dynamic random access memory (DRAM) is designed, which can calibrate the duty cycle distortion generated by external input clock and internal clock propagation, and ensure the duty cycle of output clock is close to 50%. To solve the problem that the operating frequency range of DRAM is too wide and the traditional DCC is difficult to completely cover, the clock frequency detection circuit is used in this design, and the DCC is configured with different detection accuracy and adjustment step size under high frequency and low frequency clocks, so as to realize the support for wide operating frequency range. The design is based on 19 nm memory technology and verified by post-simulation under 1.1 V supply voltage. Simulation results show that the operating frequency range of the DCC is 400 MHz to 2 GHz, the duty cycle calibration range is 40.0%-60.0%, the calibration accuracy is 50.0%±1.0%. When working at 2 GHz, the power consumption is 1.7 mW, and the output clock peak-to-peak jitter is 5.1 ps.