应用于高速模数转换器的驱动电路设计

文章针对高速模数转换器(analog-to-digital converter, ADC)的驱动需求，设计一款高速、高线性度的输入驱动缓冲器和数字输出驱动电路。在输入驱动缓冲器设计中，通过采用前馈电容的形式补偿输出端负载电容充放电过程中的瞬态电压变化，同时引入二阶效应补偿金属氧化物半导体(metal-oxide-semiconductor,MOS)管，将输入端交流变化耦合至输入对管漏端，以抑制MOS管沟道长度调制效应带来的非线性电流波动；为稳定输出信号共模电压，设计一种复制主缓冲器的共模反馈电路，为主缓冲器提供静态工作点。在数字输出驱动电路设计中，以传统电流模式低电压差分信号(low-voltage differential signaling,LVDS)驱动电路为基础，引入跳变耦合电容以加速数字信号的建立，同时设计一种带共模反馈的双电流源驱动器，使得流经匹配电阻的电流及电压更加精确。电路基于TSMC$65~\mathrm{nm}$ 工艺设计，仿真结果表明：输入驱动缓冲器在 $250\mathrm{MHz}$ 输入信号频率下，输出端采样后的信号有效位数大于10.4bit，输出共模电压波动小于 $2\mathrm{mV}$ ；数字输出驱动电路在 $500\mathrm{MHz}$ 的工作频率下，输出共模电压能够基本稳定于 $1.25\mathrm{V}$ ，输出差模电压范围为 $358\sim$ $392\mathrm{mV}$ ，均满足设计要求。

This paper focuses on the driving requirements of high-speed analog-to-digital converters (ADCs) and designs a high-speed and high-linearity input drive buffer and digital output drive circuit. For the design of input drive buffers, the transient voltage changes during the charging and discharging process of the output load capacitor are compensated by using a feedforward capacitor. At the same time, the second-order effect is introduced to compensate for the metal-oxide-semiconductor (MOS) transistor, coupling the input AC to the drain end of the input pair transistor to suppress the nonlinear current fluctuation caused by the modulation effect of MOS channel length. To stabilize the common mode voltage of the output signal, a common mode feedback circuit that replicates the main buffer is designed to provide a static working point for the main buffer. For the design of digital output drive circuits, based on the low-voltage differential signaling(LVDS) drive circuit in traditional current mode, a jump coupling capacitor is introduced to accelerate the establishment of digital signals. At the same time, a dual current source driver with common mode feedback is designed to make the current and voltage flowing through the matching resistor more accurate. The circuit design was carried out under TSMC $65~\mathrm{nm}$ technology, and simulation results showed that at an input signal frequency of $250\mathrm{MHz}$ , the effective number of bits of the sampled signal at the output end of input drive buffer was greater than 10.4 bits, and the output common mode voltage fluctuation was less than $2\mathrm{mV}$ ; the digital output drive circuit can stabilize the common mode voltage within the design range of $1.25\mathrm{V}$ , with a differential mode voltage range of $358 - 392\mathrm{mV}$ at a working frequency of $500\mathrm{MHz}$ , both of which meet the design requirements.