适用于宽带宽的快速锁定电荷泵锁相环设计

文章基于 TSMC 0.18 μm CMOS 工艺, 设计一种适用于宽带宽下可快速锁定的电荷泵锁相环 (charge pump phase-locked loop, CPPLL)。采用一种自适应快速锁定结构, 比较参考信号与反馈信号的频率、相位, 通过开启大电流与小电流快速锁定通路, 对环路滤波器中的电容进行放电使得压控振荡器的控制电压降至锁定电平附近的方法, 最大限度地减小锁定时间。通过 SPECTRE 仿真验证表明, 在 1.8 V 供电电压下, 输出频率为 768 MHz 时, 锁定时间仅需 1.5 μs, 缩短了 78%, 功耗为 3.6 mW。

Based on the TSMC 0.18 $ \mu $m CMOS technology, a charge pump phase-locked loop (CPPLL) suitable for fast locking in wide bandwidth is designed. An adaptive fast-lock structure is used to compare the frequency and phase of the reference signal with those of the feedback signal. By turning on the high current fast-lock and small current fast-lock paths, the capacitor in the loop filter is discharged so that the control voltage of the voltage controlled oscillator (VCO) drops near the lock level, thereby minimizing the locking time. SPECTRE simulation verifies that at 1.8 V supply voltage and 768 MHz output frequency, the locking time only needs 1.5 $ \mu $s, which reduces 78%, and the power consumption is 3.6 mW.