基于 USB PD 3.0 协议的新型双相标记解码电路设计与验证

文章提出一种基于 USB PD 3.0 协议的新型双相标记解码电路设计并给予验证。通过状态机控制计数器的起始与停止，实现单个数据周期突变 25% 以内的解码结果的预测和产生；通过有限长单位冲激响应滤波器计算得到解码阈值，支持对周期在增减 7.13% 范围内变化的、连续 13 个数据的解码，增大解码范围；增加完善的错误检测机制，提高电路的安全性；增加门控，空闲时关闭解码电路，节约能耗。在 Synopsys 公司的 DC 开发平台下，对电路进行仿真验证，结果表明相较参考文献中的解码电路，该文的电路结构更简单，解码准确性更高，电路面积更小，功耗更低，解码的安全性更高。

In this paper, a new biphasic mark coding (BMC) decoding circuit based on USB PD 3.0 protocol is designed and verified. Firstly, the state machine is used to control the start and stop of the counter to predict and generate the decoding result within 25% of the sudden change of the data cycle of a single data. Secondly, the decoding threshold is calculated by finite impulse response filter. It supports the successful decoding of 13 consecutive data whose cycle changes by 7.13%. Thirdly, an error detection mechanism is added to improve the safety of the circuit. Finally, the decoding circuit is turned off when idle to save energy. The circuit is simulated and verified on the DC development platform of Synopsys. Compared with the decoding circuit in the literature, the new circuit has simpler structure, higher decoding accuracy, smaller circuit area, lower power consumption and higher decoding security.