一种高速可配置二维 CFAR 检测器设计实现

恒虚警率(constant false alarm rate, CFAR)检测是雷达在干扰背景下检测目标的重要自适应算法。二维 CFAR 算法随着参考窗口尺寸增大，运算量较大，仅靠软件实现并不能满足较高的实时性需求。文章基于现场可编程门阵列(field programmable gate array, FPGA)设计实现了一种兼容 CA-CFAR、GO-CFAR、SO-CFAR 和 OS-CFAR 4 种二维 CFAR 算法的硬件加速器，同时实现标称化因子、检测器类型、排序值 K、参考窗口和保护窗口大小可配置的灵活性，对于 $ 256 \times 2048 $ 点距离-多谱勒矩阵(Range Doppler Matrix, RDM)数据，4 种检测器均可在 2.71 ms 内完成检测。设计采用全流水结构，具有高实时性。

Constant false alarm rate(CFAR) detection is an important adaptive algorithm for radar target detection under interference. With the increase of the reference window size, the two-dimensional (2D) CFAR algorithm has heavier computation. The software implementation alone cannot meet the needs of high real-time performance. Based on field programmable gate array(FPGA), this paper designs and implements a hardware accelerator compatible with four 2D CFAR algorithms: CA-CFAR, GO-CFAR, SO-CFAR and OS-CFAR. At the same time, it realizes the configurable flexibility of nominal factor, detector type, ranking value K, and reference window and protection window sizes. For $ 256 \times 2048 $ point Range Doppler Matrix(RDM) data, four detectors can complete the detection within 2.71 ms. The design adopts full pipeline structure and has high real-time performance.